LLVM and GCC are great at optimizing until the last leg of the race where they convert IR to assembly code. Their back-ends were designed for modern systems, not the ancient 6502, and so getting them to work involves kludges and clever hacks. I recall there being a video on how LLVM approaches this - search LLVM MOS on youtube.
I plan on writing an article on how my own code generator works. If you check my HN profile in a week or two you'll probably see it submitted.
In LLVM-MOS, we mainly struggle with its register allocator; the rest of the backend is really quite reasonable.
The "Greedy register allocator" in LLVM is a just finely tuned priority allocator with nice live-range splitting. It works great for zero page cache locations, but it's just not tuned very well for tight register classes like those involving the processor's three architectural registers. I've half a mind to implement Hack's SSA-based register allocator in LLVM to use on A, X, and Y; this would clean up the oodles of spurious copies LLVM-MOS spits out in the worst cases.
I plan on writing an article on how my own code generator works. If you check my HN profile in a week or two you'll probably see it submitted.